1. Field of the Invention
This invention relates to an EL display device which drives an EL element to emit light.
2. Description of Related Art
Various devices which have a plurality of scan electrodes and a plurality of data electrodes arranged in a matrix to perform display with an EL element of this type have previously been proposed. In such a matrix type display device, there is a problem where uneven luminance between columns occurs due to fluctuation in a number of pixels caused to emit light per column. The device disclosed in Japanese Unexamined Patent Publication No. Hei 7-48137 attempts to eliminate such uneven luminance by changing the pulse width of scan voltage.
However, because wiring resistance exists in scan electrodes, for the terminal voltage of the several pixels of a scan electrode, the predetermined voltage comes to be applied increasingly less as the pixel is located increasingly farther from the scan electrode terminal due to delay by wiring resistance. Because of this, even when pulse width of the scan voltage applied to the scan electrodes is controlled, as in the device described in the foregoing Japanese Unexamined Patent Publication No. Hei 7-48137, uneven luminance due to fluctuation in terminal voltage among pixels in several columns still cannot be eliminated. Delay due to wiring resistance exists even when aluminum is employed as the electrode material, and is even greater in the case of a transparent electrode composed of ITO, ZnO, or the like.
Further, to eliminate uneven luminance in each of several scan lines, the system described in Japanese Unexamined Patent Publication No. 7-48137 varies a scan signal period in accordance with a number of light-emitting pixels. This is done by controlling on and off states of switches in scan-side power supply circuits in that device to control the voltage supplied to scan-side transistors. In this case, voltages of 0 and 190 V are alternatingly applied on the line (hereinafter termed "power-supply line") connecting one of the switches to the scan-side transistors. Here, referring to "H" in FIG. 6 of Japanese Unexamined Patent Publication No. 7-48137, the time between the scan-side line (PT1) and the scan-side line (PT3) is 80 .mu.s (see PSC in the drawing), and so the cycle in which 0 V and 190 V are alternated is 12.5 kHz. When high voltage alternate in a short cycle, noise is generated, and there is a problem of interference with peripheral circuitry.